High-frequency trading is under a bright spotlight at the moment. This means more regulation may be coming and financial institutions, including hedge funds, will need to comply or risk paying heavy penalties to the regulators.
Regulators, such as the SEC in the U.S. and the European Securities and Markets Authority (ESMA) in the E.U. are under increasing pressure to bring in even more regulations that will affect the risk management strategies of both HFT firms and their trading participants.
Current market access rules such as the SECs 15C3-5 are essential to prevent so-called fat-finger errors. Software-only solutions are, however, costly to implement and they often add dozens of microseconds to every single trade and reduce competitiveness as a result. About two years ago a number of vendors, investment banks and prime brokers saw an opportunity to implement pre-trade risk rules on FPGAs. A field-programmable gate array (FPGA) is an integrated circuit that allows the client or designer to configure the circuit after its manufacture. Because of the inherent parallelism offered in FPGA architecture, these firms were able to improve on the latencies offered in equivalent software implementations. In some cases, they decreased latency by between 20 and 100 times.
Thanks to the advances in FPGA technology, it is now possible to cater to other regulations, such as MIFID II, straight on an FPGA chip. It is also possible to implement an investment firms credit limits and total aggregate volume limits on an FPGA. As new regulations kick in and as further regulations are introduced over the next few years, financial institutions will have to implement more and more risk checks. But of course no one wants to pay a linearly increasing latency penalty. This is why I believe that FPGAs will become central to pre- and post-trade risk management: in an FPGA architecture, all the checks can be implemented in a massively parallel way, vastly reducing the processing time. However, there is a trade-off to be made in terms of needing more logic real-estate on the FPGA.
We are in luck. Just like server CPU technology, FPGAs are getting bigger and faster. For example, the new Stratix 10 FPGAs from Altera will have up to 4 million logic cells, compared with 2 million logic cells in the current largest device, Virtex 7, manufactured by Xilinx. The forthcoming Stratix 10 FPGA offers advances in performance too, with core-fabric logic able to run at 1 GHz, with 10 TeraFLOPs of floating-point performance and built-in quad-core ARM A53 processor to offload the C++ trading strategies straight to the FPGA.
This sounds like holy-grail stuff so whats the catch? First, the built-in ARM processor in the FPGA is a powerful processor offering four cores. However, the latest host CPUs such as IBMs Power8 are way more powerful than anything available as built-in on the FPGAs, offering 12 cores and higher processing power.
Second, for using the FPGA core-fabric logic, you need to use programming languages such as Verilog and VHDL, and it helps to have some grounding in digital electronics, such as logic gates and flip-flops. Third, unlike software developments, where you may have a large library of functions available at your disposal, with Verilog or VHDL based designs, you have a much smaller library.
Finally, FPGA design methodology is subtly different from traditional software methodology. Targeting or mapping your design to the FPGA can take a few hours for large FPGAs.
So what is the latest thinking on the elements required to get the maximum out of FPGAs? While you may not be able to completely port the trading strategies on to the less powerful ARM processor on the FPGA, you can port the latency-critical stuff. However, with some lean-coding powerful strategies can be implemented straight onto the ARM core.
I believe you can tackle the second, third and fourth elements together by employing a team of FPGA engineers, with expertise ranging from Verilog / VHDL to simulation and targeting tools. Having an in-house library of pre-tested Verilog or VHDL functions will also help to speed up the process of starting a new design.
FPGA-based pre-trade risk management will become commonplace over the next few years. FPGAs are needed to implement the new levels of risk-management which are dictated by the current and future regulatory landscape around high-frequency trading. This is a must especially if for investment firms and brokerages that want to keep latency to a minimum and maintain that competitive edge.
Sanjay Shah is founder and CTO of Nanospeed.
